First, What Is It

• UART (Universal Asynchronous Receiver/Transmitter): a serial interface that transfers bits one by one over two wires (TX transmit, RX receive) — used by PC serial ports, sensors, and module debug ports.
• Asynchronous: there is no clock wire; both sides count bits by an agreed baud rate and frame format, so the baud rates must match.
• Why it matters: UART is the most common "log output" and debug channel in embedded development — the SDK examples all print logs at 2000000 baud for this reason.

Breaking Down the Principle

1. Frame Format: How One Byte Travels

When idle, TX stays high. Sending one byte follows this order:

• Start bit: pulls the line low so the receiver can align the following bits.
• Data bits: commonly 8 (the "8" in 8N1).
• Parity bit: optional odd/even parity for error detection (not correction).
• Stop bit: restores the line high, ready for the next frame.

"8N1" means 8 data bits, no parity (None), 1 stop bit — the default for most embedded UARTs.

2. Baud Rate: How Both Sides Count Bits

The baud rate is the number of bits transmitted per second (bit/s). The sender lays each bit on the line at that rate and the receiver samples at the same rate. If the baud rates differ, the receiver miscounts bits and sees garbage.

The baud rate is derived from a divided peripheral clock, so "changing the clock source/divider without recomputing the baud rate" also causes garbage.

3. Levels and Interface Forms

Form	Level standard	Typical scenario
TTL level	0~3.3 V/5 V	MCU directly to sensors/modules
RS-232	about ±12 V	Legacy PC serial, needs a level shifter
USB-to-serial	converter chip	PC debugging (e.g., CH340/CP2102)

The USB port on dev boards usually has a built-in USB-to-serial chip, so the PC sees a COM port while the board internally uses TTL UART.

4. Data Flow: RX Buffer and TX Buffer

MCU UART peripherals usually have a receive FIFO: incoming data is buffered first and the program reads it later; the program can also write the TX FIFO and let the hardware send it at the configured baud rate. The program never waits bit by bit.

Advanced usage:

• Interrupt reception: an interrupt fires when data arrives; the ISR collects it without blocking the main flow.
• DMA reception: hardware moves FIFO data straight into memory — the CPU is not involved, ideal for large volumes.
• Flow control (RTS/CTS): extra pins tell the peer "I'm busy / I can receive", preventing data loss.

How the SDK Implements It

• Related pages: UART (Serial), DMA Transfer, System Control Overview

SDK UART init follows the same pattern: "get device → configure baud rate → register callbacks/interrupts":

struct bflb_device_s *uart0 = bflb_device_get_by_name("uart0");
/* 2000000 baud, 8 data bits, no parity, 1 stop bit */
bflb_uart_init(uart0, 2000000, UART_DATA_LEN_8, UART_PARITY_NONE, UART_STOP_BITS_1);

The printf used for logs ultimately writes into this UART FIFO, and the hardware sends it bit by bit — so "printf works" means the UART path is healthy.

Common Exam & Interview Questions

What is 8N1?

8 data bits, no parity (None), 1 stop bit — the most common embedded serial frame format; both ends must be configured identically.

Most common causes of garbled UART output?

Different baud rates (or a changed clock/divider skewing the baud rate), swapped RX/TX wires, and missing common ground. Check the baud rate first, then the wiring.

Is UART full-duplex?

Yes. TX and RX are independent wires and can transmit and receive simultaneously — unlike I2C/SPI sharing lines in one direction at a time in some modes.

Why frame data with start/data/stop bits?

With no clock wire, the receiver uses the start bit's falling edge to align sampling; data bits carry the content; the stop bit gives a clear boundary between frames.

Difference between interrupt reception and DMA reception?

Interrupt: the CPU is interrupted on every datum to move it — fine for small amounts. DMA: hardware moves data directly to memory while the CPU stays free — better for large or high-speed transfers.

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