First, What Is It

• Interrupt: a hardware mechanism that lets events "cut in line" to notify the CPU. While the CPU is working, a button press or incoming UART data can interrupt it, be handled, and then execution resumes — like answering a ringing phone.
• Timer: a counter that ticks at a fixed rate and triggers an event (interrupt/callback) when it reaches a set value — used for delays, periodic polling, and generating PWM.
• Together: a timer expiring and raising an interrupt is the standard way to "do something every X time" in embedded systems.

Breaking Down the Principle

1. Interrupt Handling Flow

Key points:

• Vector table: a map from "which interrupt → which handler"; the hardware looks it up when the event fires.
• Save/restore context: state is saved before handling and restored afterwards, so the main program is unaffected.
• Clear the flag: the triggering flag must be cleared after handling, otherwise the interrupt re-fires endlessly.

2. Priority and Nesting

When several interrupts fire at once, hardware handles the highest priority first; a higher priority can preempt a lower one (nesting). Design rules:

• Keep ISRs short (set a flag, store data, clear the flag); do heavy work in the main loop/task.
• Never do slow operations in an ISR (long log prints, delays) — it destroys real-time behavior.
• Shared variables accessed from an ISR need atomic access on the main side (disable interrupts or use an RTOS critical section).

3. Timer Structure and Modes

A hardware timer usually contains:

• Counting source: the system clock after division.
• Prescaler: further divides the tick, controlling the counting speed.
• Counter: counts up/down from an initial value.
• Compare/reload value: triggers the interrupt (or reloads / toggles output) when reached.

Two typical modes:

Mode	Behavior	Typical use
One-shot	Triggers once and stops	Delay, timeout
Periodic	Auto-reloads and keeps triggering	Periodic sampling, heartbeat, PWM

4. Relation to Delay, PWM, and Capture

• Software delay vs timer: a while busy loop wastes CPU and is imprecise; a timer lets the CPU do other work and interrupt when the time is up.
• PWM: essentially the timer toggling an output at a fixed period; the duty cycle is the high-level share.
• Input capture: measures external pulse width/frequency by recording edge timestamps with a timer.

How the SDK Implements It

• Related pages: EXTI Interrupt, TIMER, MTimer, PWM

SDK timer-interrupt pattern: "init → register callback → start":

struct bflb_device_s *timer = bflb_device_get_by_name("timer0");
/* Register the timer ISR callback: runs timer_isr when it expires */
bflb_timer_attach_irq(timer, timer_isr);
bflb_timer_init(timer, TIMER_PRESCALER_256, TIMER_COUNTER_INCREASE, 0xffffffff);
bflb_timer_set_compvalue(timer, 1000000);   /* Trigger at 1000000 counts */
bflb_timer_start(timer);

External interrupts (EXTI) configure a GPIO as interrupt input and bind a callback — a button press triggers via hardware instead of polling.

Common Exam & Interview Questions

Why must ISRs avoid long operations?

An ISR preempts the main flow; long operations block other interrupts and tasks, destroying real-time behavior. Keep ISRs short: set flags, store data, clear flags.

Why clear the interrupt flag after handling?

If the flag stays set, hardware thinks the event still exists and immediately re-triggers the interrupt — the main program never gets to continue.

Software delay vs timer delay?

Software delay busy-waits, wasting CPU and being affected by optimization; a timer counts in hardware, letting the CPU run other tasks and interrupt when done — more accurate and efficient.

What decides PWM period and duty cycle?

Period: counting frequency and the reload value. Duty: the compare value — the output toggles/drops when the counter reaches it, so changing the compare value changes the duty cycle.

Is "priority inversion" an interrupt topic?

Priority inversion belongs to RTOS task scheduling (a low-priority task holding a lock blocks a high-priority task); interrupts themselves only have hardware priority, where higher priority can preempt (nest) lower ones.

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